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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.2
- 발행연도
- 2023.4
- 수록면
- 89 - 97 (9page)
- DOI
- 10.5573/JSTS.2023.23.2.89
이용수
초록· 키워드
오류제보하기
This paper presents a simple timing-skew calibration circuit for time-interleaved ADCs. At the core of the skew calibration scheme lies a pair of D flip-flops to detect the sign of the relative timing between a channel clock and the reference clocks. The D flip-flops form a latch structure to detect the sign of timing skew. The detected sign of the timing skew is accumulated by counters and used to control shunt-capacitor- inverter variable delay lines to adjust the timing of the channel clocks. Although this scheme cannot remove the skew from mismatches after the timing comparison point, it should be able to reduce the bulk of the timing skew. The performance of the calibration circuit implemented using a 28 nm CMOS technology was verified by post-layout simulations.
목차
Abstract
I. INTRODUCTION
II. PROPOSED FLIP-FLOP BASED TIMING SKEW CALIBRATION METHOD
III. SIMULATION RESULTS
IV. DISCUSSIONS AND CONCLUSIONS
REFERENCES
참고문헌 (11)
참고문헌 신청
J. Son and Y. Jang, “A 10-bit 10-MS/s Asynchronous SAR ADC with Input Offset Calibration using Capacitor DAC,” J. Semiconductor Technology and Science, Vol. 20, No. 6, pp. 518-525, Dec. 2020.
I. Yeo and B. Lee, “A 12-bit 40 MS/s SAR ADC with Digital Foreground Self-calibration for Capacitor Mismatches,” J. Semiconductor Technology and Science, Vol. 20, No. 01, pp. 105-118, Feb. 2020.
L. Kull et al., “A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS,” in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013, doi: 10.1109/JSSC.2013.
M. El-Chammas and B. Murmann, “General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 902-910, May 2009, doi: 10.1109/TCSI.2009. 2015206.
S. Lee, A. P. Chandrakasan and H. Lee, “22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 384-385, doi: 10.1109/
I. Yeo and B. Lee, “A 12-bit 40 MS/s SAR ADC with Digital Foreground Self-calibration for Capacitor Mismatches,” J. Semiconductor Technology and Science, Vol. 20, No. 01, pp. 105-118, Feb. 2020.
L. Kull et al., “A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS,” in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013, doi: 10.1109/JSSC.2013.
M. El-Chammas and B. Murmann, “General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 902-910, May 2009, doi: 10.1109/TCSI.2009. 2015206.
S. Lee, A. P. Chandrakasan and H. Lee, “22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 384-385, doi: 10.1109/
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