지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.6
- 발행연도
- 2021.12
- 수록면
- 472 - 482 (11page)
- DOI
- 10.5573/JSTS.2021.21.6.472
이용수
초록· 키워드
오류제보하기
A 2<SUP>nd</SUP>-order Noise-Shaping ADC using a 2-bit/cycle SAR ADC is proposed. With a designated reference DAC and a signal DAC, three comparators in the SAR ADC enable 2-bit conversion in each comparison cycle. The noise transfer function (NTF) of the ADC is implemented in an error-feedback structure to bypass the need for power-consuming integrator. A low-gain switched input/output openloop residue amplifier and a switched-capacitor FIR filter realizes the NTF coefficients. The proposed ADC was designed with a 28-nm CMOS process with 1-V power supply. The SPICE simulation results show that the designed ADC has SNDR of 69.9 dB and power consumption of 4.08 mW, when operated with a sampling rate of 320-MS/s and OSR of 8 achieving a Walden figure-of-merit (FoM) of 39.9-fJ/conv.-step.
목차
Abstract
I. INTRODUCTION
II. PROPOSED 2B/CYCLE-NS-SAR ADC
III. CIRCUIT DESCRIPTION
IV. SIMULATION RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (16)
참고문헌 신청
S. Lim, J. Woo Kim, K. Yoon and S. Lee, “A 12-b Asynchronous SAR Type ADC for Bio Signal Detection,” J. Semiconductor Technology and Science, Vol. 13, No. 2, pp. 108-113, Feb. 2013.
B. Kim, L. Yan, J. Yoo and H.-J. Yoo, “A 40fJ/c-s1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology,” J. Semiconductor Technology and Science, Vol. 11, No. 1, pp. 23-32, Jan. 2011.
J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp. 2898-2904, Dec. 2012, doi: 10.1109/JSSC. 2012.2217874.
Z. Chen, M. Miyahara and A. Matsuzawa, "A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noiseshaping SAR ADC," Digest of 2015 Symp. on VLSI Circuits, pp. C64-C65, doi: 10.1109/VLSIC.2015.7231329.
S. Li, B. Qiao, M. Gandara, D. Z. Pan and N. Sun, "A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure," IEEE J. of Solid-State Circuits, Vol. 53, No. 12, pp. 3484-3496, Dec. 2018, doi: 10.1109/JSSC.2018.2871081.
B. Kim, L. Yan, J. Yoo and H.-J. Yoo, “A 40fJ/c-s1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology,” J. Semiconductor Technology and Science, Vol. 11, No. 1, pp. 23-32, Jan. 2011.
J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp. 2898-2904, Dec. 2012, doi: 10.1109/JSSC. 2012.2217874.
Z. Chen, M. Miyahara and A. Matsuzawa, "A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noiseshaping SAR ADC," Digest of 2015 Symp. on VLSI Circuits, pp. C64-C65, doi: 10.1109/VLSIC.2015.7231329.
S. Li, B. Qiao, M. Gandara, D. Z. Pan and N. Sun, "A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure," IEEE J. of Solid-State Circuits, Vol. 53, No. 12, pp. 3484-3496, Dec. 2018, doi: 10.1109/JSSC.2018.2871081.
이 논문의 저자 정보
이 논문과 함께 이용한 논문
A Simple Timing-skew Calibration using Flip-flops for Time-interleaved ADCs
Ji-Hun Lim
,
Sang-Gyu Pa
,
k
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2023
.04
우수-기수 모드 해석을 통한 표면 실장 소자의 기생 성분 계산 방법
양기성
,
민병욱
한국전자파학회논문지
2023
.01
A 12-b Asynchronous SAR Type ADC for Bio Signal Detection
Shin-Il Lim
,
Jin Woo Kim
,
Kwang-Sub Yoon
외 1명
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2013
.04
최근 본 자료
댓글(0)
0