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논문 기본 정보

자료유형
학술저널
저자정보
Chang Choo (San Jose State University) Young-Uk Chang (San Jose State University) Il-Young Moon (Korea University of Technology)
저널정보
한국정보통신학회JICCE Journal of information and communication convergence engineering Journal of information and communication convergence engineering Vol.13 No.3
발행연도
2015.9
수록면
145 - 151 (7page)

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초록· 키워드

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We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

목차

Abstract
I. INTRODUCTION
II. BACKGROUND
III. DESIGN DESCRIPTION
IV. ANALYSIS AND VERIFICATION OF RESULTS AND PERFORMANCE
V. CONCLUSION
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