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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.4
- 발행연도
- 2020.8
- 수록면
- 390 - 404 (15page)
- DOI
- 10.5573/JSTS.2020.20.4.390
이용수
초록· 키워드
오류제보하기
With advancements in process technology and ever-increasing complexity of digital circuits, testing has become a prominent problem. The lengthy scan chains used for testing semiconductor chips cause not only the longer test time but also excessive test power consumption. Such excessive test power (especially peak power during shifting) can cause reliability degradation for the semiconductor. To resolve this problem, we introduce an exclusive shiftin and shift-out method along with a scan chain reordering algorithm. The proposed method is evaluated with several benchmark circuits including ISCAS’89, ITC’99 and IWLS’05. The results indicate that the proposed technique reduces the average power and helps mitigating the peak power consumption. In addition, an optimization method is introduced to reduce the area overhead of proposed scan technique. As a result, area overhead of proposed scan architecture was reduced to 1-11%.
목차
Abstract
I. INTRODUCTION
II. RELATED WORKS
III. PROPOSED SCAN TEST METHOD
IV. COMPATIBILITY OF THE PROPOSED SCAN TEST METHOD WITH ADVANCED SCAN TEST TECHNIQUES
V. EXPERIMENTAL RESULTS
VI. CONCLUSIONS
REFERENCES
참고문헌 (28)
참고문헌 신청
K. Butler, J. Saxena, A. Jain, T. Fryars, J. Lewis, G. Hetherington, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” IEEE International Test Conference, pp. 355-364, 2004.
Y. Li, W. Lien, I. Lin, K. Lee, Capture-power-safe test pattern determination for at-speed scan-based testing, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 127-137, 2014.
X. Lin and Y. Huang, “Scan shift power reduction by freezing power sensitive scan cells,” Journal of Electronic Testing, vol. 24, no. 4, pp. 327-334, 2008.
Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in Proc. IEEE VLSI Test Symposium, 1993, pp. 4-9.
L. Wang, C. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, San Francisco, CA, USA: Elsevier, 2006
Y. Li, W. Lien, I. Lin, K. Lee, Capture-power-safe test pattern determination for at-speed scan-based testing, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 127-137, 2014.
X. Lin and Y. Huang, “Scan shift power reduction by freezing power sensitive scan cells,” Journal of Electronic Testing, vol. 24, no. 4, pp. 327-334, 2008.
Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in Proc. IEEE VLSI Test Symposium, 1993, pp. 4-9.
L. Wang, C. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, San Francisco, CA, USA: Elsevier, 2006
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