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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2019.11
- 수록면
- 1,449 - 1,457 (9page)
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This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.
목차
Abstract
I. INTRODUCTION
II. STACKING TOPOLOGIES
III. SIMULATION AND EXPERIMENTAL RESULTS
IV. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
R. C. Chu, R. E. Simons, M. J. Ellsworth, R. R. Schmidt, and V. Cozzolino, “Review of cooling technologies for computer products,” IEEE Trans. Device Mater. Rel., Vol. 4, No. 4, pp. 568-585, Dec. 2004.
K. M. Attia, M. A. El-Hosseini, and H. A. Ali, “Dynamic power management techniques in multi-core architectures: A survey study,” Ain Shams Eng. J., Vol. 8, No. 3, pp. 445-456, Sep. 2017.
P. T. Krein, “A discussion of data center power challenges across the system,” in 2010 International Conference on Energy Aware Computing, pp. 1-3, 2010.
P. Jain, T. Kim, J. Keane, and C. H. Kim, “A multi-story power delivery technique for 3D integrated circuits,” in Proceeding of the 13th international symposium on Low power electronics and design (ISLPED ’08), pp. 57-62, 2008.
S. Rajapandian, Zheng Xu, and K. L. Shepard, “Implicit DC-DC downconversion through charge-recycling,” IEEE J. Solid-State Circuits, Vol. 40, No. 4, pp. 846-852, Apr. 2005.
K. M. Attia, M. A. El-Hosseini, and H. A. Ali, “Dynamic power management techniques in multi-core architectures: A survey study,” Ain Shams Eng. J., Vol. 8, No. 3, pp. 445-456, Sep. 2017.
P. T. Krein, “A discussion of data center power challenges across the system,” in 2010 International Conference on Energy Aware Computing, pp. 1-3, 2010.
P. Jain, T. Kim, J. Keane, and C. H. Kim, “A multi-story power delivery technique for 3D integrated circuits,” in Proceeding of the 13th international symposium on Low power electronics and design (ISLPED ’08), pp. 57-62, 2008.
S. Rajapandian, Zheng Xu, and K. L. Shepard, “Implicit DC-DC downconversion through charge-recycling,” IEEE J. Solid-State Circuits, Vol. 40, No. 4, pp. 846-852, Apr. 2005.
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