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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2005.1
- 수록면
- 431 - 438 (8page)
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초록· 키워드
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In this paper, we propose the built-in current testing circuit for improving reliability. As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability. In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.
목차
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참고문헌 (19)
참고문헌 신청
/ 1984. / Characteri- zation and testing of physical failures in MOS logic circuits 1 : 76 ~
/ 1987. / Realistic fault modeling for VLSI testing : 173 ~
/ 1988. / A CMOS fault extractor for inductive fault analysis 7 (11) : 1181 ~
/ 1989. / A self-testing ALU using built-in current sensing : 2211 ~
/ 1990. / CMOS bridging faults detection : 842 ~
/ 1987. / Realistic fault modeling for VLSI testing : 173 ~
/ 1988. / A CMOS fault extractor for inductive fault analysis 7 (11) : 1181 ~
/ 1989. / A self-testing ALU using built-in current sensing : 2211 ~
/ 1990. / CMOS bridging faults detection : 842 ~
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