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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2006.1
- 수록면
- 507 - 511 (5page)
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초록· 키워드
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We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from 7 ㎛ to 15 ㎛. As the polysilicon-2 thickness increased up to 1000 Å, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer.
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등록된 정보가 없습니다.
참고문헌 (8)
참고문헌 신청
/ 1979. / Alpha-particle tracks in silicon and their effect on dynamic MOS RAM reliability ed-26 : 10 ~
/ 1985. / Alpha-particle-induced charge collection measurements and the effectiveness of a novel p-Well protection barrier on VLSI memories ed-32 (1) : 49 ~
/ 1987. / Influences on soft error rates in static RAM's sc-22 (3) : 430 ~
/ 1989. / Improvement of soft-error rate in MOS SRAM's 24 (4) : 860 ~
/ 1990. / New well structure for deep sub-μm CMOS/BiCMOS using thin epitaxy over buried layer and trench isolation Symposium on VLSI Technology : 83 ~
/ 1985. / Alpha-particle-induced charge collection measurements and the effectiveness of a novel p-Well protection barrier on VLSI memories ed-32 (1) : 49 ~
/ 1987. / Influences on soft error rates in static RAM's sc-22 (3) : 430 ~
/ 1989. / Improvement of soft-error rate in MOS SRAM's 24 (4) : 860 ~
/ 1990. / New well structure for deep sub-μm CMOS/BiCMOS using thin epitaxy over buried layer and trench isolation Symposium on VLSI Technology : 83 ~
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