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논문 기본 정보

자료유형
학술저널
저자정보
Ji Hun Jang (Inha University) Sunwoong Kim (Seoul National University) Chae Eun Rhee (Inha University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.6
발행연도
2017.12
수록면
832 - 844 (13page)
DOI
10.5573/JSTS.2017.17.6.832

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초록· 키워드

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Currently, frame memory compression (FMC) is widely adopted in video codecs. To store high-resolution video frames in external memory, the bus access time and the memory space are significant overheads for real-time video processing. There are many previous works which focus on data compression rates. However, in an actual system, several modules, including the video codec and the external memory, are connected via a system bus. In this environment, the gain in compression and the gain in transfer are very different. For a practical FMC design, not only the compression rate but also the transfer efficiency should be carefully considered. In this paper, a bus-aware interface design for one dimensional (1D) lossless FMC is proposed to reduce the amount of bus transfers. The proposed bitstream merging and tailed burst length schemes increase the transfer gain such that it is close to the gain in compression. The proposed 1D lossless FMC schemes are implemented in Verilog language and verified in an environment containing a high efficiency video coding (HEVC) encoder and a system bus.

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Abstract
I. INTRODUCTION
II. THE TARGET SYSTEM ENVIRONMENT
III. THE PROPOSED BUS-AWARE FMC INTERFACE DESIGN
IV. PERFORMANCE EVALUATION OF THE PROPOSED BUS-AWARE INTERFACE DESIGN
V. HARDWARE IMPLEMENTATION
VI. CONCLUSION
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