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Subject

A Jitter Characteristic Improved PLL with RC Time Constant Circuit
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저항-커패시턴스 시정수 회로를 이용하여 지터 특성을 개선한 위상고정루프

논문 기본 정보

Type
Academic journal
Author
Seong-Jin An (부경대학교) Yong-Shig Choi (부경대학교)
Journal
The Institute of Electronics and Information Engineers Journal of the Institute of Electronics and Information Engineers Vol.54 No.2 (Wn.471) KCI Excellent Accredited Journal
Published
2017.2
Pages
133 - 138 (6page)

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Topic
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Method
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Result
A Jitter Characteristic Improved PLL with RC Time Constant Circuit
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Abstract· Keywords

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This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF’s voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

Contents

요약
Abstract
Ⅰ. 서론
Ⅱ. 제안된 위상고정루프 회로
Ⅲ. 회로 설계
Ⅳ. 측정 결과
Ⅴ. 결론
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UCI(KEPA) : I410-ECN-0101-2017-569-002249377