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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.2
- 발행연도
- 2014.4
- 수록면
- 189 - 197 (9page)
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This work proposes a 12b 100 MS/s 0.11 μm CMOS three-step hybrid pipeline ADC for highspeed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dualchannel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a 0.11 μm CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of 1.34 mm² and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT DESCRIPTION
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (21)
참고문헌 신청
1. [학술지(정기간행물)] - B. W. Koo / 2011 / A single amplifier-based 12-bit 100MS/s 1V 19mW 0.13μm CMOS ADC with various power and area minimized circuit techniques / IEICE Trans. on Electronics E94-C (8) : 1282 ~ 1288
2. [학술대회논문] - C. Jack / 2010 / A zero-crossing based 12b 100MS/s pipeline ADC with decision boundary gap estimation calibration / Symp. VLSI Circuits Dig. Tech. Papers : 237 ~ 238
3. [학술지(정기간행물)] - Y. J. Kim / 2009 / A 0.31pJ/conversion-step 12-bit 100MS/s 0.13μm CMOS A/D converter for 3G communication system / IEICE Trans. on Electronics E92-C (9) : 1194 ~ 1200
4. [학술대회논문] - T. Ito / 2006 / 55-mW 1.2-V 12-bit 100-MSps pipelined ADCs for wireless receivers / Proc. Eur. Solid-State Circuits Conf. : 540 ~ 543
5. [학술지(정기간행물)] - C. Grace / 2005 / A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration / IEEE J. Solid-State Circuits 40 (5) : 1038 ~ 1046
2. [학술대회논문] - C. Jack / 2010 / A zero-crossing based 12b 100MS/s pipeline ADC with decision boundary gap estimation calibration / Symp. VLSI Circuits Dig. Tech. Papers : 237 ~ 238
3. [학술지(정기간행물)] - Y. J. Kim / 2009 / A 0.31pJ/conversion-step 12-bit 100MS/s 0.13μm CMOS A/D converter for 3G communication system / IEICE Trans. on Electronics E92-C (9) : 1194 ~ 1200
4. [학술대회논문] - T. Ito / 2006 / 55-mW 1.2-V 12-bit 100-MSps pipelined ADCs for wireless receivers / Proc. Eur. Solid-State Circuits Conf. : 540 ~ 543
5. [학술지(정기간행물)] - C. Grace / 2005 / A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration / IEEE J. Solid-State Circuits 40 (5) : 1038 ~ 1046
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