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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2010.10
- 수록면
- 1,678 - 1,681 (4page)
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초록· 키워드
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This paper proposes a window-based image processing architecture that minimizes data activities. This architecture has a mapping structure between the line buffer and the window buffer. Each buffer handler writes or reads pixel data in one direction. This feature allows the designer to use a FIFO memory, as well as dual port random memory in the proposed architecture. Thus, the designer can select buffer types as per design efforts. We use this architecture to implement a dynamic threshold circuit. In order to meet time constrains, the output is processed by the pipeline method to meet time constraints. The pipeline method incurs output latency. The Sync Generator module is added to the implemented circuit to synchronize processed image information. Experiments show the logic quality of the circuit implemented circuit using the proposed architecture.
목차
Abstract
1. INTRODUCTION
2. THE WINDOW ARCHITECTURE
3. THE PROPOSED WINDOW-BASED ARCHITECTURE
4. IMPLEMENTATION OF DYNAMIC THRESHOLD
5. CONCLUSION
6. ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000940057