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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 1,109 - 1,112 (4page)
이용수
이 논문의 연구 히스토리 (3)
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초록· 키워드
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As an asynchronous design method, TiDE tool chain supports the robust design flow at a high level with an asynchronous specialized language, HASTE. However, there is a limitation at an optimized step, since it is difficult for designers to know and manage inner synthesis operations. With a button-up manner based on the synthesis method with asynchronous finite state machine (AFSM), we design an asynchronous MSP430 core which is widely used in the sensor nodes.
The designed asynchronous MSP430 core was compared with an already designed asynchronous MSP430 core which employed the TiDE tool flow and a clock based synchronous MSP430 core at 0.13 um CMOS technology. The maximum performance of the TiDE tool version was only 40.6 % of the synchronous or the AFSM version. The AFSM version saves the energy consumption of the synchronous version and the TiDE tool version by about 31.9 % and 28.8 %, respectively.
The designed asynchronous MSP430 core was compared with an already designed asynchronous MSP430 core which employed the TiDE tool flow and a clock based synchronous MSP430 core at 0.13 um CMOS technology. The maximum performance of the TiDE tool version was only 40.6 % of the synchronous or the AFSM version. The AFSM version saves the energy consumption of the synchronous version and the TiDE tool version by about 31.9 % and 28.8 %, respectively.
목차
Abstract
1. Introduction
2. Asynchronous Design
3. Architecture of Asynchronous MSP430 Core
4. Design and Simulation Result
Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2013-569-001141290