2-D DCT Using Multiplierless Reconfigurable Arithmetic Arrays

JeongEun Kim ,  SangKyu Lee ,  Namsub Kim 외 2명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

A Study on Multiplierless Digital Neuron

In Jung Pa ,  k ,  Min Hwa Pa 외 1명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1994 .01

The Implementation of Multiplierless Digital Neural Network

Jae Young Pa ,  k ,  Cheon Woo Lee 외 2명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1995 .01

Multiplierless FIR여파기의 설계에 관한 연구 ( A Study on the Design of Multiplierless FIR Filters )

신재호 ,  이종각

전자공학회논문지

1986 .03

Multiplierless Digital Architecture for Membership Function Evaluation

G. C. Ca ,  da ,  illi 외 3명

ICONIP : International Conference On Neural Information Processing

1994 .01

Multiplierless Digital PID Controller Using FPGA

So ,  awat Chivap ,  eecha 외 9명

제어로봇시스템학회 국제학술대회 논문집

2004 .08

A New Multiplierless Digital Synapse with Parallel Data Addressing

In Jung Pa ,  k

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1996 .01

Multiplierless Digital Architecture for Membership Fuction Evaluation

G. C. Ca ,  da ,  ill 외 3명

ICONIP : International Conference On Neural Information Processing

1994 .01

Development of a Run-Time Reconfigurable System using Partially Reconfigurable FPGA

Isao Sakamoto ,  Takano ,  i Susaki 외 9명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

MCM(Multiple Constant Multiplication)과 폴딩 방식을 이용한 Multiplierless 웨이블릿 변환 구조

김지원 ,  손창훈 ,  이배호 외 1명

대한전자공학회 학술대회

2010 .11

동적 재구성 구조의 하드웨어 활용도를 높이기 위한 Processing Element의 설계

이재익 ,  김진상 ,  조원경 외 1명

한국통신학회 학술대회논문집

2004 .11

Reconfigurable Co-synthesis System Architecture

Ji-han Pa ,  k ,  Sang-hoon Kwak 외 3명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

An Hardware-Effective Multiplierless FIR Filter Chip with Variable-Length Taps

Sung Hyun Yoon ,  Myung H. Sunwoo

ICVC : International Conference on VLSI and CAD

1997 .01

A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 ㎛ CMOS

Yasuhi ,  o TAKAHASHI ,  Toshikazu SEKINE 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

An Implementation of Video Streaming Processing on a Dynamically Self-Reconfigurable System

Hidetomo Shibamu ,  a ,  Take 외 9명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

Development of Optimization Algorithm for Solving Reconfigurable Planning Problem in RMS

K. A. Ku ,  niadi ,  K. Y. Ryu 외 1명

한국정밀공학회 학술발표대회 논문집

2017 .12

Design and Implementation of Multiplierless FIR Digital Filter Using Logarithmic Numbering System Technique

S. Chivap ,  eecha ,  K. Dejhan

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2003 .07

A New Lossless/Lossy Image Coding based on A Multiplierless Integer DCT

Somcha ,  t CHOKCHAITAM ,  Masahi 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2006 .07

재구성 가능 공작기계 설계를 위한 인터넷 기반 시뮬레이터 개발

홍동표 ,  서윤호

대한산업공학회지

2006 .06

Design Reconfigurable 2-D Systolic Array Using Pseudo Faulty Processing Element

Dong Suk Shin ,  Bong Jo Choo ,  Chong Ho Woo

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1995 .01