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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ICEIC : International Conference on Electronics, Informations and Communications ICEIC : 2008
- 발행연도
- 2008.6
- 수록면
- 190 - 193 (4page)
이용수
초록· 키워드
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This paper proposes a floating gate non-volatile memory cell that operates at lowered voltage by about 75% when compared to that of flash memory. Voltage required for Fowler-Nordheim tunneling is reduced by half when the stacked polysilicon memory cell is unfolded and spread onto a planar cell structure in which one MOS capacitor is much larger than another. The voltage is further decreased, again by half, if vertical and horizontal voltages are bootstrapped at the intersection. Since the high voltage is localized at tunneling MOS capacitor in the memory cell, all other transistors are free from device deterioration induced by long term high voltage stressing. The internally upconverted power supply voltage is low enough for the charge pump to has improved efficiency and consequently to save power consumption. The memory cell was implemented in the embedded memory of the passive RFID tag, and it is under fabrication using 0.18㎛ full CMOS technology.
목차
Abstract
1. Introduction
2. Floating Gate Type NVM Cells
3. Low Voltage NVM Cell
4. Simulation
5. Conclusions
Acknowledgments
References
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