지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ICEIC : International Conference on Electronics, Informations and Communications ICEIC : 2008
- 발행연도
- 2008.6
- 수록면
- 147 - 150 (4page)
이용수
초록· 키워드
오류제보하기
The novel frequency doubling technique proposed in this paper shifts by 90° an oscillation signal and its inverted signal, both having 50% duty cycle. The technique then performs AND operations on the two pairs of the original and shifted signals, providing an oscillation signal and its 180° out-of-phase signal, both having 25% duty cycle but retaining the same frequency. The technique finally performs an OR operation on these signals to synthesize an oscillation signal having 50% duty cycle and a doubled frequency. Since a differential ring-oscillator can generate inverted and shifted signals, the frequency doubling technique can be easily realized using a differential ring-oscillator followed by AND and OR logic. In this paper the proposed technique has been implemented using a 4-stage differential oscillator with differential latched inverters and NAND gates for AND and OR operations. The resulting circuit has been simulated using H-SPICE based on the 0.18 ㎛ 1.8 V TSMC CMOS library for functional verification and performance results. While the 4-stage differential oscillator operates at 1.87 ㎓ with the power consumption of 0.643 ㎽, the overall circuit produces the output signal of oscillating at 3.74 ㎓ with 0.762 ㎽ consumed. Finally, the ADS simulation of the circuit shows that the phase noise is -87.17 ㏈c/㎐ for the ring-oscillator and -82.57 ㏈c/㎐ for the overall circuit, both at 1 ㎒ offset.
목차
Abstract
1. Introduction
2. Doubling Oscillation Frequency
3. Simulation Results
4. Conclusions
References
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