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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ICEIC : International Conference on Electronics, Informations and Communications ICEIC : 2010
- 발행연도
- 2010.6
- 수록면
- 548 - 551 (4page)
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초록· 키워드
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In this paper, high performance 2-D 8x8 forward integer transform architecture is proposed. The proposed transform has two types of architectures. One is high throughput transform architecture, the other is hardware sharing transform architecture. Based on matrix operations with Kronecker product and direct sum, the high throughput 2-D 8x8 forward transform can be derived from the 1-D 8x8 forward transform. Using the high throughput transform architecture with hardware sharing method, hardware sharing transform architecture can be implemented. The proposed high throughput transform architecture has 66% higher throughput. The proposed hardware sharing transform architecture has about 21% lower computational complexity.
목차
Abstract
Ⅰ. Introduction
Ⅱ. 8×8 Transform Algorithm
Ⅲ. Hardware Implementation
Ⅳ. Synthesis Results and Comparison
Ⅴ. Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2012-569-004078074