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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.10 No.1
- 발행연도
- 2010.3
- 수록면
- 66 - 77 (12page)
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초록· 키워드
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Improvement in breakdown voltage (BVds) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length (L<SUB>g</SUB>), but due to lithographic limitation, shortening L<SUB>g</SUB> below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate on to the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the BVds of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in BV<SUB>ds</SUB> can be obtained by applying field plates, especially at the drain side. The important parameters affecting BVds and cut-off frequency (f<SUB>T</SUB>) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, Γ-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. THEORETICAL CONSIDERATIONS
Ⅲ. DEVICE REALIZATION AND CHARACTERIZATION
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2010-569-002142562