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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.8 No.2
- 발행연도
- 2008.6
- 수록면
- 134 - 138 (5page)
이용수
초록· 키워드
오류제보하기
We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. POWER GATING STRUCTURE
Ⅲ. GROUND BOUNCE NOISE REDUCTION
Ⅳ. TEST CIRCUITRY AND EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (10)
참고문헌 신청
1. [학술지(정기간행물)] - H. Mahmoodi-Meimand / 2004 / A leakagetolerant high fanin dynamic circuit design style / IEEE Transactions on Circuits and Systems-I 51 (3) : 495 ~ 503
2. [단행본] - S. G. Narendra / 2006 / Leakage in Nanometer CMOS Technologies / Springer
3. [학술지(정기간행물)] - S. Mutoh / 1995 / 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS / IEEE Journal of Solid-State Circuits SC-30 : 847 ~ 854
4. [학술지(정기간행물)] - S. Shigematsu / 1997 / A 1-V high-speed MTCMOS circuit scheme for power-down application circuits / IEEE Journal of Solid-State Circuits SC-32 : 861 ~ 869
5. [학술대회논문] - K. Kumagai / 1998 / A novel powering-down scheme for low Vt CMOS circuits / Proc. of the IEEE Symposium on VLSI Circuits : 44 ~ 45
2. [단행본] - S. G. Narendra / 2006 / Leakage in Nanometer CMOS Technologies / Springer
3. [학술지(정기간행물)] - S. Mutoh / 1995 / 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS / IEEE Journal of Solid-State Circuits SC-30 : 847 ~ 854
4. [학술지(정기간행물)] - S. Shigematsu / 1997 / A 1-V high-speed MTCMOS circuit scheme for power-down application circuits / IEEE Journal of Solid-State Circuits SC-32 : 861 ~ 869
5. [학술대회논문] - K. Kumagai / 1998 / A novel powering-down scheme for low Vt CMOS circuits / Proc. of the IEEE Symposium on VLSI Circuits : 44 ~ 45
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