지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.2 No.6
- 발행연도
- 1997.10
- 수록면
- 208 - 211 (4page)
이용수
초록· 키워드
오류제보하기
We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-level gate and located ~100A right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-blockade oscillation is demonstrated at 15 mK and its periodicity of 16.4 mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7 aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Experiment
Ⅲ. Results and Discussion
Ⅳ. Summary
Acknowledgements
References
저자소개
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Dual Gate-Controlled SOI Single Electron Transistor : Fabrication and Coulomb-Blockade
Journal of Electrical Engineering and information Science
1997 .12
-
Single Electron Transistors With Dual Gate Structure
대한전자공학회 학술대회
1998 .01
-
Coupling Characteristics of Semiconductor Quantum Dots in Coulomb Blockade Regime
International Conference on Electronics, Informations and Communications
1998 .01
-
Gate Tunneling Current and Quantum Effects in Deep Scaled MOSFETs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2004 .03
-
다중 게이트를 이용한 SOI Thin Film Transistor의 특성에 관한 연구
한국재료학회 학술발표대회
1997 .01
-
Analysis of Tunnelling Rate Effect on Single Electron Transistor
Journal of Electrical Engineering & Technology
2014 .09
-
Fabrication of in-Plane Gated Transistor with Electron-Beam lithography Technique
대한전자공학회 학술대회
1997 .01
-
Electron Injection Characteristics of an Adaptive Device Using a Split-Gate MOS Transistor
대한전자공학회 학술대회
1998 .01
-
Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .02
-
Insulated Gate Transistor의 설계 및 제작 ( Design and Fabrication of the Insulated Gate Transistors )
대한전자공학회 학술대회
1987 .11
-
Oscillation Phase 의 조절이 가능한 SONOS 구조를 가진 이중-게이트 단 전자 트랜지스터
대한전자공학회 학술대회
2010 .06
-
Fabrication of Molecular Single Electron Tunneling Device
KIEE International Transactions on Electrophysics and Applications
2002 .04
-
A New SOI inverter Gate for Low Power Applications
대한전자공학회 학술대회
1996 .01
-
New Dynamic Logic Gate Design Method for Improved TFT Circuit Performance
Journal of information display
2005 .01
-
Threshold Voltage control of Pentacene Thin-Film Transistor with Dual-Gate Structure
한국정보디스플레이학회 International Meeting
2006 .01
-
Top and Bottom Gate Voltage Dependent Tunneling Current of Asymmetric DGMOSFET
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2015 .06
-
Characteristics of Gate Structure in Junctionless Double Gate Field Effect Transistors
대한전자공학회 학술대회
2019 .06
-
시뮬레이션을 통한 이중 게이트 Tunneling Field Effect Transistor의 Compact Modeling
대한전자공학회 학술대회
2016 .06
-
DG-SET 성능 향상을 위한 공정 방법
대한전자공학회 학술대회
2008 .11
-
나노 스케일 SOI MOSFET를 위한 소자설계 가이드라인
전자공학회논문지-SD
2002 .07
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2009-569-017765247