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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.2 No.4
- 발행연도
- 1997.8
- 수록면
- 8 - 13 (6page)
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초록· 키워드
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This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicate in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. It has the initial latency of N+3 cycles with N×N array configuration. We designed an experimental 200 ㎒ 4Kb static RAM chip with the 4×4 array configuration of 256b SRAM blocks. It was fabricated in 0.8㎛ twin-well single-poly double-metal CMOS technology.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Architecture
Ⅲ. Circuit Implementation
Ⅳ. Experimental Results
Ⅴ. Conclusions
References
저자소개
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UCI(KEPA) : I410-ECN-0101-2009-569-017764604