INTEGRATED ENVIRONMENT FOR HIGH-SPEED INTERCONNECT MODELING

Soo Young Oh ,  Ken Lee ,  Kent Okasaki

ICVC : International Conference on VLSI and CAD

1989 .01

Discontinuous RC Interconnect Line Analysis for Accurate Timing Determination

Taehoon Kim ,  Youngdoo Song ,  Yungseon Eo

대한전자공학회 ISOCC

2008 .11

Time Domain Sensitivity of High-Speed VLSI Interconnects

Nelson Liu ,  Michel S. Nakhia ,  Qi Jun Zhang

ICVC : International Conference on VLSI and CAD

1993 .01

반도체 회로 연결선의 신뢰도 해석을 위한 전류 해석 기법

김기영 ,  임재호 ,  김석윤

전기학회논문지

2010 .08

Performance Estimation of High-Speed Backplane Interconnects

Jaeha Kim ,  Vladimi ,  M. Stojanović

대한전자공학회 ISOCC

2004 .10

Flow Control in High Speed Backbone Interconnecting LANs

Seong Ho Jeong ,  Hyun Kook Kahng ,  Jang Kyung Kim 외 1명

Asia-Pacific Conference on Communications

1993 .01

An Integrated Environment for Electrical Modeling and Characterization of Packages and Interconnects in High-Speed VLSI System

Soo-Young Oh

JOURNAL OF KIEE

1990 .03

Modeling Guideline on the Minimum Number of Segments for Interconnect Current Estimation

Ki-young Kim ,  Jae-Ho Lim ,  Sung-Bin Kim 외 1명

ICEIC : International Conference on Electronics, Informations and Communications

2010 .06

SIMS: Circuit Interconnect Modeling Environment for VLSI Design

차건업 ,  정원영 ,  김용배 외 2명

대한전자공학회 학술대회

1994 .07

Timing Analysis of Discontinuous RC Interconnect Lines

Taehoon Kim ,  Youngdoo Song ,  Yungseon Eo

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2009 .03

도선 모델링 ( Interconnect Modeling ) 기술

박홍준 ,  김찬경 ,  박종훈 외 1명

전자공학회지

1997 .12

SIMS ( SPICE Interconnect Modeling System ) for VLSI design

정원영 ,  차건업 ,  김용배 외 2명

대한전자공학회 학술대회

1994 .01

Experimental Characterization-Based Signal Integrity Verification of Sub-Micron VLSI Interconnects

Yung-seon Eo ,  Young-jun Pa ,  k 외 3명

Journal of Electrical Engineering and Information Science

1997 .10

신뢰성 해석을 위한 반도체 다중연결선의 RMS 전류 추정 기법

김기영 ,  김덕민 ,  김석윤

전기학회논문지

2011 .08

CAD Models and Verification of Integrated Circuit Interconnects

어영선

대한전자공학회 학술대회

1996 .01

CAD Models and Verification of Integrated Circuit Interconnects

Yungseon Eo

대한전자공학회 학술대회

1996 .05

Traffic Generator Model을 이용한 On-Chip Interconnect IP 성능 검증

김기범 ,  조성민 ,  송용호

대한전자공학회 학술대회

2009 .07

Parasitic Capacitance Modeling for On-Chip Interconnects

Yoshihi ,  o Uchida ,  Sadahi 외 4명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2003 .07