상태 정보 학습에 기반을 둔 순차형 ATPG 알고리즘

이재훈 ,  송오영

한국통신학회 학술대회논문집

1998 .11

ATPG 가속화를 위한 분할 기법의 설계

허덕행

한국컴퓨터정보학회논문지

1998 .06

An Implementation of a Universal ATPG for VLSI Digital Circuits

Hak Soo Kim ,  Jong Kwon Chang

International Conference on Electronics, Informations and Communications

1993 .01

An Implementation of a Universal ATPG For VLSI Digital Circuits

Hak-Soo ,  Kim ,  Jong-Kwon 외 1명

ICEIC : International Conference on Electronics, Informations and Communications

1993 .08

Sequential 회로를 위한 ATPG

김석원 ,  조경순 ,  김광현

전자공학회지

1993 .11

Labeling Scheme for Fault Simulation of Combinational Circuits

Han Heung Kim ,  S. H. Hwang ,  Chong Min Kyung

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1991 .01

상태 정보 학습을 이용한 새로운 순차회로 ATPG 기법 ( New Test Generation for Sequential Circuits Based on State Information Learning )

이재훈 ,  송오영

한국통신학회논문지

2000 .04

Output Signal Probability from a Combinational Circuit

Byung Ho Jo ,  Hee Yeung Hwang

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1990 .01

조합논리회로의 결합검출 ( Fault Detection in Combinational Circuits )

고경식 ,  허웅

전자공학회지

1974 .11

On the Correction of Multiple Design Errors in Combinational Logic Circuits

I ,  ith Pome ,  anz 외 2명

ICVC : International Conference on VLSI and CAD

1993 .01

CMOS VLSI의 IDDQ 테스팅을 위한 ATPG 구현 ( Implementation of ATPG for IDDQ Testing in CMOS VLSI )

김강철 ,  류진수 ,  한석붕

전자공학회논문지-A

1996 .03

CMOS 조합 논리 회로에서의 빠른 천이 예측 기법 ( Fast and Accurate Estimation of the Transitions of CMOS Combinational Circuits )

박영수 ,  조한진 ,  이성봉 외 2명

대한전자공학회 워크샵

1996 .01

多値 組合論理回路의 故障診斷에 관한 硏究

임인칠 ,  이재민

(구)정보과학회논문지

1981 .11

A Study of Cooling Schemes for the Generation of Input Pairs of CMOS Combinational Circuits Using the Simulated Annealing Algorithm

Albe ,  to Palacios Pawlovsky ,  Hi 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

유전알고리즘을 이용한 조합회로용 테스트패턴의 고장검출률 향상 ( Fault Coverage Improvement of Test Patterns for Combinational Circuit using a Genetic Algorithm )

박휴찬

Journal of Advanced Marine Engineering and Technology (JAMET)

1998 .09

Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits

Isao Tsukimoto ,  Masaki Hashizume ,  Yukiko Mushiaki

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2002 .07

부울 미분을 이용한 다치 논리 회로에서의 결함 해석 ( Fault Analysis in Multivalued Combinational Circuits Using the Boolean Difference Concept )

류광렬 ,  김종상

전자공학회지

1981 .02

ON THE SPEEDING UP OF THE SIMULATED ANNEALING ALGORITHM IN GENERATING INPUT PAIRS FOR CMOS COMBINATIONAL CIRCUITS

Albe ,  to Palacios Pawlovsky ,  Masato Ha 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2006 .07

조합논리회로의 결함검출시험에 관한 연구 ( A Study on Fault Detection Tests for Combinational Logic Networks )

최흥문

전자공학회지

1978 .01

부울 미분을 이용한 다치 논리회로의 결함해석 ( Fault Analysis in Multivalued Combinational Circuits Using The Boolean Difference Concept )

유광렬 ,  김종상

대한전자공학회 학술대회

1980 .01