SEA-OF-GATES

김진구

CAD기술특강

1989 .01

A Hierarchical Placement Algorithm for Building Block Layout Design

Byung Ik Kang ,  Jong Wha Chong

ICVC : International Conference on VLSI and CAD

1991 .01

A HIERARCHICAL ALGORITHM FOR GATE MATRIX LAYOUT

Kazuhi ,  o Yamazaki ,  Shoichi 외 2명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

An Improved Hierarchical Placement Technique Using Clustering & Region Refinement

Won Jong Kim ,  Ki Taek Kim ,  Hyun Chul Shin

대한전자공학회 기타 간행물

1996 .01

A PERFORMANCE-DRIVEN HIERARCHICAL PLACEMENT SYSTEM BASED ON DYNAMIC NET-WEIGHT ADJUSTMENT

Won Jong Kim ,  Hyun Chul Shin

ICVC : International Conference on VLSI and CAD

1995 .01

16d_b 정착길이를 가지는 대구경 확대머리철근의 2단 배근에 대한 정착강도

천성철 ,  심혜정 ,  이병수

한국콘크리트학회 학술대회 논문집

2018 .05

직접회로의 새로운 계층적 배치 기법 ( A New Method for Hierarchical Placement of Integrated Circuits )

김충희 ,  신현철

전자공학회논문지-A

1993 .06

FAST SIMULATED ANNEALING PLACEMENT COMBINED WITH INITIAL PLACEMENT METHOD

Masahi ,  o Mitsuyasu ,  Victo 외 4명

ICVC : International Conference on VLSI and CAD

1989 .01

A New Placement Algorithm for Gate Array Considering I / O Pads and Macrocells

Byung Il Kang ,  Jong Wha Chong

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1988 .01

A useful approach in the placement runtime and memory improvement of big cloned hierarchical top-down designs

Satyana ,  ayana M V V ,  Rajend 외 2명

대한전자공학회 ISOCC

2005 .10

새로운 게이트 어레이 배치 알고리듬 ( A New Placement Algorithm for Gate Array )

강병익 ,  정정화

전자공학회논문지

1989 .05

2-bit/Cell Split Gate Flash Memory with Double Gate

2-bit/Cell Split Gate Flash Memo ,  y with Double Gat ,  Il Han Pa 외 5명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2007 .07

Three-dimensional Placement Considering Number of Modules

Katsumi Ha ,  ashima ,  Dai Matsuu 외 3명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2004 .07

Gate Array

오용협

전자공학회지

1992 .06

Hierarchical Attractive and Repulsive Force-Directed Placement Method

Kazuhi ,  o Ueda ,  Victo 외 2명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1994 .01

A METHOD OF IMPLEMENTING MIN-CUT PLACEMENT FOR Q-TAT LAYOUT DESIGN OF LARGE SCALE GATE ARRAYS

Kazuhi ,  o Takahashi ,  Yasuhi 외 4명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

3-Dimentional Block Placement of Force Directed Model with Cluster Growth

Hideyuki Tanaka ,  Katsumi Ha ,  ashima

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2007 .07

3-Level Gate Drive Design

노재석 ,  배기훈 ,  강호현 외 1명

전력전자학회 학술대회 논문집

2018 .07

STUDIES ON FABRICATION TECHNIQUES OF SUB-0.4μm T-GATE AND Γ-GATE STRUCTURES USING UV LITHOGRAPHY

Il Hyeong Lee ,  Sung Soo Kim ,  Yeon Sik Chae 외 2명

ICVC : International Conference on VLSI and CAD

1995 .01

a-Si Gate 구동회로의 Stepwise Gate 신호적용에 대한 연구

명재훈 ,  곽진오 ,  이준신

전기전자재료학회논문지

2008 .01