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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
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- 학위논문
- 저자정보
- 지도교수
- 류지열
- 발행연도
- 2023
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이 논문의 연구 히스토리 (3)
2023
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In the near decade, countless signals and information are being exchanged for the growing demands of 5G in our daily lives. There is also phenomenal development in integrated circuits, and those are used for this massive amount of information in various types of devices.
Our speech is an analog signal, but digital signals are found in electronic components. However, digital signals cannot be directly interpreted by humans, so a data converter is required.
This paper presents a 12-bit successive approximation register(SAR) analog-to-digital converter(ADC). The proposed SAR ADC consists of a sample-and-hold stage, a network capacitor array stage, a SAR control logic stage, a comparator stage, a DAC control logic stage and a DAC stage.
In an addition, the ADC is also being used to convert the processed digital signal back into an analog signal, and it is equipped with capacitors, resistors, and computational amplifiers to retrieve the original signal.
The proposed circuit is designed by using the 1poly-6metal 0.13µm CMOS process, and it operates at a supply voltage of 1.2V. In contrast with traditional performance, the designed ADC showed a very low power consumption of 60.07µW and the smallest die area of 0.???mm2 as compared to conventional results. This circuit also exhibits an outstanding effective number of bits(ENOB) of 12.02bits and high signal-to-noise distortion ratio(SNDR) of 74.17dB. Furthermore, the sample-and-hold stage which is placed at the front end of the SAR ADC is developed to reduce the body effect, and one input clock is intended to minimize unnecessary power consumption and operation.
Our speech is an analog signal, but digital signals are found in electronic components. However, digital signals cannot be directly interpreted by humans, so a data converter is required.
This paper presents a 12-bit successive approximation register(SAR) analog-to-digital converter(ADC). The proposed SAR ADC consists of a sample-and-hold stage, a network capacitor array stage, a SAR control logic stage, a comparator stage, a DAC control logic stage and a DAC stage.
In an addition, the ADC is also being used to convert the processed digital signal back into an analog signal, and it is equipped with capacitors, resistors, and computational amplifiers to retrieve the original signal.
The proposed circuit is designed by using the 1poly-6metal 0.13µm CMOS process, and it operates at a supply voltage of 1.2V. In contrast with traditional performance, the designed ADC showed a very low power consumption of 60.07µW and the smallest die area of 0.???mm2 as compared to conventional results. This circuit also exhibits an outstanding effective number of bits(ENOB) of 12.02bits and high signal-to-noise distortion ratio(SNDR) of 74.17dB. Furthermore, the sample-and-hold stage which is placed at the front end of the SAR ADC is developed to reduce the body effect, and one input clock is intended to minimize unnecessary power consumption and operation.
목차
제 1장 서론 1제 2장 동작원리 32-1 일반적인 ADC의 동작 및 구조 32-2 ADC의 주요 성능 변수 및 수식 62-3 SAR ADC의 동작 및 구조 8제 3장 제안된 SAR ADC 회로 및 동작원리 133-1 샘플 앤 홀드 단 133-2 커패시터 어레이 네트워크 단 163-3 비교기 단 193-4 SAR 로직 단 213-5 DAC 제어 로직 단 233-6 DAC 단 243-7 제안하는 SAR ADC 26제 4장 결과 및 고찰 284-1 시뮬레이션 결과파형 분석 284-2 주요 성능변수 평가 35제 5장 결론 38참고문헌 39별 첨 44
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