목차

Table of Contents
1.Introduction .......................................................................................................1
2. ADC Architectures ..........................................................................................3
2.1 SAR ADC .......................................................................................................3
2.2 Sigma Delta ADC ...........................................................................................7
2.3 Flash ADC.......................................................................................................8
2.4 Pipeline ADC .................................................................................................9
3. ADC Performances........................................................................................10
3.1 Quantization Noise와 SNR ..........................................................................10
3.2 SNDR and ENB ............................................................................................11
3.3 SFDR(Spurious-Free Dynamic Range) .....................................................11
3.4 DNL (Differential Non-Linearity) Error ...................................................11
3.5 INL (Integral Non-Linearity) Error ..........................................................13
3.6 Offset Error .................................................................................................14
3.7 Gain Error ....................................................................................................15
4. Proposed SAR ADC .......................................................................................16
4.1 Top Block & Timing Diagram .....................................................................16
4.2 CDAC ...........................................................................................................19
4.3 Custom Designed Capacitor.........................................................................22
4.4 Dynamic Latched Comparator.....................................................................23
4.5 Reference Voltage Generator......................................................................25
4.6 Rail-to-Rail Input Buffer ...........................................................................27
5. Simulation Result ...........................................................................................28
5.1 Dynamic Latched Comparator .....................................................................29
5.2 Reference Voltage Generator .....................................................................30
5.3 Rail-to-Rail Input Buffer ...........................................................................33
5.4 Top Simulation .............................................................................................34
5.5 Top Layout ..................................................................................................36
6. Conclusion .......................................................................................................35
References ..........................................................................................................36