Silicon physical unclonable function (PUF) is one of the most desirable circuits for security chip in resource-constrained environment such as internet of things applications. This thesis presents a reconfigurable SRAM-based PUF topology with multiple challenge-response pairs (CRPs) in a cell. The proposed PUF structure enables a very large CRP space by connecting additional pull-up and pull-down paths to each SRAM cell. These alternate pathways to the supply rail and ground are activated by the challenge inputs, which effectively reconfigure the transfer characteristics of each cross-coupled inverter. A newly proposed response instability detector improves bit error rate (BER) performance by discarding unstable response. In addition, the proposed PUF adds indirect challenges by scrambling the responses using a Galois linear feedback shift register (LFSR). The proposed PUF can be applied to a wider range of applications as a CRP PUF because it has multiple CRPs in addition to the small area and fast operating speed, which are the advantages of the conventional SRAM structure. In order to verify the performance of the proposed architecture, a 32×32-bit reconfigurable SRAM PUF array with 32-bit challenge is implemented in a 65 nm CMOS process. Experimental results show a core area of 88.867 μm2/bit, energy efficiency of 0.082 pJ/bit, and inter-chip Hamming distance (HD) of 48.93% across 40 chips. By applying the response instability detector scheme, BER is improved from 13.7% to 0.9%. The response scrambler increases prediction error for modeling attack through machine learning algorithm from 16.6% to 23.9% when 104 CRPs are trained. Compared to the state-of-the-art, the proposed PUF is shown to be highly competitive in area, throughput and energy efficiency.