In this thesis, a high performance elliptic curve cryptography(HP-ECC) processor was designed, which supports five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2. HP-ECC processor supports eight operation modes including ECPSM, ECPA, ECPD, MA, MS, MM, MI, MD. In addition, the designed HP-ECC processor adopts the modified left-to-right binary algorithm for scalar multiplication and this algorithm is resistant to side-channel attacks because it calculates the same point addition and point doubling regardless of the Hamming weight of private key. Modular multiplication consists of integer multiplication and reduction steps and was implemented using Karatsuba-Ofman multiplication, Lazy reduction, and Nikhilam division algorithm. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. A 264 bits multiplier, 640, and 1280 bits carry select adder were used to perform internal operations, and HP-ECC processor was designed to store input data and intermediate operation results in registers without using memory for high speed operation.
The HP-ECC processor was verified by functional verification using Vivado design suite and RTL simulation results are compared with Python software results. The computation of ECPSM for field size of 256 bits takes 28,315 clock cycles, and for field size of 521 bits takes 188,794 clock cycles. The HP-ECC processor synthesized using a 180 nm CMOS cell library occupies 620,846 gate equivalents (GEs) at 67 MHz clock frequency, and the estimated maximum clock frequency is 91 MHz.