As Internet of Things (IoT) technology develops rapidly, the importance of information security is increasing. Therefore, public key cryptography, which is useful for key management and authentication, must be used. The elliptic curve cryptography (ECC) public key cryptography provides similar stability with shorter key lengths than RSA public key cryptography.
In this thesis, a DF-ECC processor was designed to be lightweight for devices with limited hardware resources. The DF-ECC processor supports dual field elliptic curves of prime field and binary field as defined by the SEC2 standard, and can also support elliptic curves defined in other standard. The DF-ECC processor minimizes the finite field arithmetic circuit for lightweight design. In elliptic curve cryptography, finite field arithmetic is finite field addition, subtraction, XOR, multiplication, squaring, division, inversion. The finite field squaring was replaced by the designed finite field multiplication, and the finite field division was eliminated by suing the projective coordinate, and the finite field inversion was implemented by applying the Fermat’s little theorem to the defined finite field multiplication. Therefore, the DF-ECC processor was implemented by finite field addition, subtraction, XOR, and multiplication. The finite field arithmetic circuit was designed with a 32-bit data-path over dual field. The finite field multiplication was designed using word based Montgomery multiplication algorithm and can support various key lengths with fixed hardware. In addition, the DF-ECC processor can apply to various standards because the parameters used in the word-based Montgomery multiplication algorithm can be internally generated by designed arithmetic circuit.
The DF-ECC processor was verified by functional verification using ModelSim and FPGA implementation. It was synthesized using a 180-nm CMOS cell library, and it occupies 21,846 gate equivalents (GEs) and 11-Kbits RAM at 100 MHz, and the estimated maximum clock frequency is 100 MHz. With Xilinx FPGA it occupies 1,128 slices and 1 BRAM and the estimated maximum clock frequency is 55 MHz. It supports a variety of elliptic curves and mode of operation and was implemented with a small area that is suitable for use as a public key cryptography for information security in limited hardware devices.