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논문 기본 정보

자료유형
학위논문
저자정보

박범준 (충남대학교, 忠南大學校 大學院)

지도교수
박동철
발행연도
2015
저작권
충남대학교 논문은 저작권에 의해 보호받습니다.

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이 논문의 연구 히스토리 (2)

초록· 키워드

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Modern wideband intercept systems demand wideband input characteristic, high speed signal detection, fine frequency tuning, and high dynamic range in order to intercept unfriendly radar systems which have complex modulation characteristics and short operating time. This paper presents the design method of a wideband high speed frequency synthesizer which is an essential part of the modern wideband intercept system.
In order to realize a modern intercept system, wideband frequency synthesizer must have fast settling time, fine frequency resolution, allowable frequency accuracy and phase noise, and minimum spurious performance all together. Conventional DTO(Digital Tuned Oscillator) has fast settling time, but it has poor phase noise and frequency accuracy. On the other hand, analog frequency synthesizer has very fast settling time and good phase noise performance, but it is expensive to achieve fine frequency resolution. Indirect frequency synthesizer using PLL(Phased-Lock Loop) can offer wideband output and good phase noise, but it has slower frequency settling time than DTO having 1 ㎲ settling time.
In this dissertation, a 6~13 GHz high speed frequency synthesizer having minimum 30 kHz step size and minimum 500 ns frequency settling time is proposed. In order to obtain fast settling time, fine resolution, and good phase noise performance, wideband output frequencies were synthesized based on DDS and analog direct frequency synthesis technology. The DDS having octave band is very important for implementation of wideband synthesizer, because the frequency coverage of DDS output can be easily extended with frequency multipliers, wideband mixer, and switched filter banks. Spurious analysis for frequency plan design was performed and phase noise requirements of DDS and local oscillators, and 2.4 GHz PLL part were respectively derived from phase noise requirement of frequency synthesizer.
Since the hybrid frequency synthesizer in this dissertation requires frequency source with fine resolution and fast settling time, therefore, a wideband DDS module covering the frequency range from 0.5 to 1.1 GHz was designed and fabricated. The clock frequency of the DDS was selected as 2.4 GHz in order for 600 MHz output bandwidth. Multiple spurious cancelling signals having same amplitude and 180 ° phase difference compared to the spurious were created at the additional path and added to the output signal within DDS for the spurious performance improvement. The fabricated DDS module showed better more than 10 dB spurious performance than a commercial DDS one and the measured frequency settling time was below 310 ns.
Also, in order to obtain good phase noise and frequency accuracy performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked to the stable 100 MHz reference oscillator using SPD(Sampling Phase Detector). The phase noise performance of the 2.4 GHz PLL was estimated and the results were compared with the measured ones. The measured phase noise of the 2.4 GHz PLL was less than ?131 dBc @ 100 kHz at 2.4 GHz. And the measured frequency accuracy of 2.4 GHz PLL was about 300 Hz.
Finally, the performance of the fabricated hybrid frequency synthesizer was measured. The measured frequency settling time was below 500 ns, the phase noise was below ?106 dBc @ 10 kHz at 13 GHz, and the frequency accuracy was measured below ± 2 kHz. The phase noise performance of the hybrid frequency synthesizer was estimated by the superposition theory. It was found that the estimated phase noise was similar to the measured one. The measured spurious performance was below ?50 dBc, and the frequency resolution was measured below 30 kHz.
The advantage of hybrid frequency synthesizer proposed in the dissertation is the wideband output bandwidth, the high speed settling time, the fine resolution, the high frequency stability, and the good phase noise and spurious performance. Therefore, this kind of synthesizer can be usefully applied to modern wideband intercept systems as well as jammers which require high performance synthesizer in the near future.

목차

제 1 장 서 론 1
제 1 절 연구 배경 1
제 2 절 연구 목표 및 연구내용 요약 3
제 3 절 논문의 구성 6
제 2 장 하이브리드 구조의 광대역 고속 주파수 합성기 8
제 1 절 전파 모니터링 장비 구조 8
제 2 절 광대역 고속 주파수 합성기 설계 10
2.2.1 기존의 광대역 주파수 합성기 구조 10
2.2.2 광대역 고속 주파수 합성기 구조 및 설계 요소 분석 14
2.2.3 주파수 플랜 20
2.2.4 위상잡음원 모델링 및 요구 성능 도출 37
제 3 장 Feedforward 기법을 적용한 광대역 DDS 42
제 1 절 불요신호 성능 개선을 위한 광대역 DDS 구조 42
3.1.1 기본 주파수 합성부 44
3.1.2 보조 주파수 합성부 46
제 2 절 DDS 불요신호 제거 시뮬레이션 54
제 3 절 광대역 DDS 제작 및 측정 결과 57
제 4 장 SPD를 이용한 2.4 GHz 아날로그 PLL 65
제 1 절 2.4 GHz PLL 구조 65
제 2 절 위상잡음 예측 67
제 3 절 루프 필터 설계 74
제 4 절 2.4 GHz PLL 제작 및 측정 결과 79
제 5 장 주파수 합성기 제작 및 측정 84
제 1 절 제작 및 측정 결과 84
제 2 절 결과 고찰 98
제 6 장 결 론 101
참고 문헌 104
ABSTRACT 109

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