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논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 정진균
- 발행연도
- 2015
- 저작권
- 전북대학교 논문은 저작권에 의해 보호받습니다.
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초록· 키워드
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FFT/IFFT is one of the key components in the efficient implementation of OFDM systems since FFT/IFFT processors require large amount of area. To improve the performances of FFT/IFFT processors, many FFT/IFFT algorithms have been proposed to reduce the computational complexities, including radix-2, radix-4, split-radix, radix-22, radix-24 and so on. For high-throughput applications, pipeline FFT/IFFT architectures are often adopted. Among the various pipelined IFFT/FFT architectures, the single-path delay feedback(SDF) approach based on the radix-22 algorithm is frequently used for its low cost and high efficiency.
In N-point SDF IFFT/FFT design, the required number of the total feedback memory locations is (N-1). In addition, the bit-reversal part requires 2xN memory locations for reordering data sequences. Note that the required memory size in bit-reversal part nearly doubles the size of the feedback memory in SDF IFFT/FFT architectures. In large point IFFT design, the memory size occupies more than 70% of the chip area. Thus, it is important to reduce the memory cells required in the design of IFFT/FFT.
This thesis focuses on reducing the size of memory cells of IFFT in OFDM systems. Proposed selected mapping algorithm adopts Radix-22 algorithm and DIT-based architecture. It is shown that the memory cells in bit-reversal and stages 1 and 2 are efficiently reduced using the selected mapping method. It is also shown that about 58% memory cells can be reduced by the proposed method.
The proposed structure can be successfully applied to WLAN(DIT architecture). Also, the proposed structure is expected to be helpful to the design and implementation of various high speed OFDM systems.
In N-point SDF IFFT/FFT design, the required number of the total feedback memory locations is (N-1). In addition, the bit-reversal part requires 2xN memory locations for reordering data sequences. Note that the required memory size in bit-reversal part nearly doubles the size of the feedback memory in SDF IFFT/FFT architectures. In large point IFFT design, the memory size occupies more than 70% of the chip area. Thus, it is important to reduce the memory cells required in the design of IFFT/FFT.
This thesis focuses on reducing the size of memory cells of IFFT in OFDM systems. Proposed selected mapping algorithm adopts Radix-22 algorithm and DIT-based architecture. It is shown that the memory cells in bit-reversal and stages 1 and 2 are efficiently reduced using the selected mapping method. It is also shown that about 58% memory cells can be reduced by the proposed method.
The proposed structure can be successfully applied to WLAN(DIT architecture). Also, the proposed structure is expected to be helpful to the design and implementation of various high speed OFDM systems.
목차
제 1장 서론 1제 2장 FFT/IFFT 알고리즘 3제 3장 제안하는 IFFT 구조 21제 4장 시뮬레이션 37제 5장 결론 42
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