지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 조성익
- 발행연도
- 2013
- 저작권
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In modern digital audio applications, the demands for high-resolution and low-power ADCs(Analog to Digital Converters) have increased. Among various ADCs, the Sigma-Delta ADC with the noise-shaping and oversampling technique is widely used for low-power and high-resolution data converters.
In this thesis, a third-order Sigma-Delta Modulator with CIFB(Cascade of Integrators FeedBack) architecture is designed for low-power consumption. The modulator consists of two integrators. And a CIFB architecture is used to ensure stable operation and low-power consumption.
In the first integrator, a low power SC(Switched-Capacitor) integrator can reduce the power consumption of the operational amplifier. And an operational amplifier sharing technique is applied to the second integrator. This technique reduces the number of amplifiers. Also in input signal, delayed feed-forward path minimizes the output swing of noise-sensitive first integrator. Thus, the optimized coefficients of the first integrator reduce the number of capacitors.
In this thesis, modeling and simulation of the modulator was performed by MATLAB and Spectre. The modulator was designed using the 0.18um CMOS process and the power supply voltage of 1.8V, input signal of 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz are set as the simulation environment. The simulation results of the designed Sigma-Delta modulator are an SNR(Signal to Noise Ratio) of 88.9dB and an ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the Sigma-Delta modulator is 180㎼ and the chip area is 556㎛×600㎛ (0.33㎟).
In this thesis, a third-order Sigma-Delta Modulator with CIFB(Cascade of Integrators FeedBack) architecture is designed for low-power consumption. The modulator consists of two integrators. And a CIFB architecture is used to ensure stable operation and low-power consumption.
In the first integrator, a low power SC(Switched-Capacitor) integrator can reduce the power consumption of the operational amplifier. And an operational amplifier sharing technique is applied to the second integrator. This technique reduces the number of amplifiers. Also in input signal, delayed feed-forward path minimizes the output swing of noise-sensitive first integrator. Thus, the optimized coefficients of the first integrator reduce the number of capacitors.
In this thesis, modeling and simulation of the modulator was performed by MATLAB and Spectre. The modulator was designed using the 0.18um CMOS process and the power supply voltage of 1.8V, input signal of 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz are set as the simulation environment. The simulation results of the designed Sigma-Delta modulator are an SNR(Signal to Noise Ratio) of 88.9dB and an ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the Sigma-Delta modulator is 180㎼ and the chip area is 556㎛×600㎛ (0.33㎟).
목차
목 차 Ⅰ그 림 목 록 Ⅲ표 목 록 ⅤABSTRACT Ⅵ1. 서 론 12. Sigma-Delta 변조기 개요 32.1. Analog to Digital Converter(ADC) 종류 32.2. Analog to Digital Conversion 과정 52.3. 오버샘플링 Sigma-Delta ADC 72.3.1. 양자화 잡음 72.3.2. 오버샘플링 원리 112.3.3. 잡음변형(Noise shaping) 원리 143. 저전력 3차 Sigma-Delta 변조기 설계 193.1. 저전력 Sigma-Delta 변조기 설계배경 193.2. Sigma-Delta 변조기 구조 223.3. Sigma-Delta 변조기 저전력 기법 243.3.1. 저전력 스위치드-커패시터 적분기 243.3.2. 연산증폭기 공유 기법 273.3.3. 지연된 피드포워드 경로 293.4. Sigma-Delta 변조기 모델링 313.5. Sigma-Delta 변조기 회로설계 343.5.1. 연산증폭기 설계 353.5.2. CMFB 설계 393.5.3. 비교기 설계 413.5.4. 클록 발생기 설계 433.5.5. 스위치 설계 464. 모의실험 및 레이아웃 495. 결 론 54참 고 문 헌 56
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