지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 박홍준
- 발행연도
- 2014
- 저작권
- 포항공과대학교 논문은 저작권에 의해 보호받습니다.
이용수0
이 논문의 연구 히스토리 (3)
2014
- 이 논문의 후속연구가 궁금하신가요?
- 연관 학술논문 또는 학술발표를 통해 보다 발전된 연구결과를 확인하실 수 있습니다.
- 이 논문의 연구 히스토리 확인하기
초록· 키워드
오류제보하기
In this paper, A USB 2.0 full-speed device is implemented in FPGA by using a Verilog synthesis. Full-speed device consists of Physical layer (PHY), Serial Interface Engine (SIE), and Device Specific Logic (DSL).
Full-speed PHY works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX, The TX and RX circuits include a NRZI encoder/decoder, a bit sutffer/unstuffer, and serializer/deserializer. The clock generator accepts a 60MHz clock and generates five 12MHz clock signals which are spaced uniformly in time and synchronized to the 60MHz clock. The five 12MHz clocks are enable signals of TX and RX circuits. The 60MHz clock is used as the clock signal of the TX and RX circuits. The 60MHz clock are used for blind oversampling of CDR. An external 1.5kΩ resistor is connected between the D+ node and VDD to notify the connection of the device PHY to the host PC.
Full-speed SIE and DSL are implemented for USB 2.0 full-speed device. It works successfully in a Xilinx Vertex-5 FPGA chip at the data rate of 12Mbps for a mouse application.
Full-speed PHY works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX, The TX and RX circuits include a NRZI encoder/decoder, a bit sutffer/unstuffer, and serializer/deserializer. The clock generator accepts a 60MHz clock and generates five 12MHz clock signals which are spaced uniformly in time and synchronized to the 60MHz clock. The five 12MHz clocks are enable signals of TX and RX circuits. The 60MHz clock is used as the clock signal of the TX and RX circuits. The 60MHz clock are used for blind oversampling of CDR. An external 1.5kΩ resistor is connected between the D+ node and VDD to notify the connection of the device PHY to the host PC.
Full-speed SIE and DSL are implemented for USB 2.0 full-speed device. It works successfully in a Xilinx Vertex-5 FPGA chip at the data rate of 12Mbps for a mouse application.
목차
등록된 정보가 없습니다.
최근 본 자료
댓글(0)
0