This thesis presents 10-bit 20-MS/s CMOS asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) with the features of low power consumption and small area. Generally, an asynchronous SAR ADC is an architecture that has the higher conversion rate compared with a synchronous SAR ADC architecture and consumes the lower power compared with a synchronous pipeline ADC architecture.
Firstly, an asynchronous SAR ADC is designed to improve sampling rate a 10-bit 10-MS/s. It consists of a split capacitor-based digital-to-analog converter (SC-DAC), a time-domain comparator, and a SAR logic. By using the structure of split capacitor, the DAC which has an area of large portion in the total area has low power and small area. The time-domain comparator takes a advantage of small variation at offset voltage and noise in comparison with voltage comparator. To achieve high performance of SAR ADC, the comparator has a offset calibration circuit. The designed ADC was implemented by using 0.18-μm CMOS process with 1.8 V supply voltage, the area and power consumption are 0.062 mm2 and 1.27 mW. For the input frequency of 101.12 kHz, the measured SNDR (signal-to-noise and distortion ratio) and ENOB (effective number of bit) are 55.5 dB and 8.9-bit, respectively.
Secondly, a 10-bit 20-MS/s asynchronous SAR ADC is proposed. It consists of a binary weighted DAC, a comparator with a meta-stability detection circuit, and a SAR logic. The proposed meta-stability detection circuit prevents the data conversion error due to the meta-stability in a comparator. The LSB (least significant bit) capacitor in the binary weighted DAC is implemented by using two unit capacitor connected in series. The SAR logic is optimized by using a variable delay line. The designed ADC was fabricated by using 65-nm CMOS process with 1 V supply voltage. The measured SNDR for the input frequency of 101.7 kHz is 56.91 dB and the ENOB is 9.16-bit. The active area and power consumption are 0.0783 mm2 and 0.46 mW, respectively. The FoM (figure of merit) which presents the performance index of the ADC is 43 fJ/conversion-step.