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논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 조성익
- 발행연도
- 2013
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As CMOS process technology and data processing performance develops, a high-speed interface circuit is in high demand. In general, serial-link is applied for high-speed data communications as the interface standard, which is widely adapted in many wired communication areas. The Clock and Data Recovery(CDR) circuit is one of the key blocks for low power in a receiver.
This dissertation presents a low power all digital CDR covering data rates from 600Mbps to 1.5Gbps. The dual loop CDR based on interpolator consists of clock generator for multi-phase clock and CDR loop.
A charge pumped PLL generates 16-phase clock from 8-stage differential ring oscillator. The PLL consists of Phase Frequency Detector(PFD), Charge Pump(CP), Loop Filter(LF) and Divider.
The interpolation CDR was replaced phase rotator(PR) and 3-state alexander PD in order to overcome the disadvantages of phase interpolator(PI).
Furthermore, sampler stage reduced the number of flip-flops from 48 to 30 for the low power in the multi-bit alexander PD. It is made possible by adjusting the input data of PD’s DN section and PR control. The CDR consists of sampler stage, Phase Error Detector(PED), Digital Filter(DF), PR and PR Finite State Machine(FSM).
The proposed CDR was fabricated with 0.13um CMOS standard process and was verified to be operational at data rates from 600Mbps to 1.5Gbps. The peak-to-peak clock jitter of the clock generator is 24ps at 750MHz, and the peak-to-peak and RMS jitter of recovered data is 389ps and 34ps at 1.5Gbps. The size of the implemented chip is 1183μm by 973μm and the power consumption of the PLL and CDR is 27mW, 5mW respectively.
This dissertation presents a low power all digital CDR covering data rates from 600Mbps to 1.5Gbps. The dual loop CDR based on interpolator consists of clock generator for multi-phase clock and CDR loop.
A charge pumped PLL generates 16-phase clock from 8-stage differential ring oscillator. The PLL consists of Phase Frequency Detector(PFD), Charge Pump(CP), Loop Filter(LF) and Divider.
The interpolation CDR was replaced phase rotator(PR) and 3-state alexander PD in order to overcome the disadvantages of phase interpolator(PI).
Furthermore, sampler stage reduced the number of flip-flops from 48 to 30 for the low power in the multi-bit alexander PD. It is made possible by adjusting the input data of PD’s DN section and PR control. The CDR consists of sampler stage, Phase Error Detector(PED), Digital Filter(DF), PR and PR Finite State Machine(FSM).
The proposed CDR was fabricated with 0.13um CMOS standard process and was verified to be operational at data rates from 600Mbps to 1.5Gbps. The peak-to-peak clock jitter of the clock generator is 24ps at 750MHz, and the peak-to-peak and RMS jitter of recovered data is 389ps and 34ps at 1.5Gbps. The size of the implemented chip is 1183μm by 973μm and the power consumption of the PLL and CDR is 27mW, 5mW respectively.
목차
목 차 Ⅰ그 림 목 록 Ⅲ표 목 록 ⅤABSTRACT Ⅵ1. 서 론 12. 클록 데이터 복원회로의 기본 이론 32.1. PLL 방식의 클록 데이터 복원회로 52.2. 블라인드 오버 샘플링 방식의 클록 데이터 복원회로 62.3. 보간 방식의 클록 데이터 복원회로 72.4. 기존 보간 방식의 클록 데이터 복원회로 82.4.1. 위상 보간 회로 82.4.2. 위상 검출기 103. 전디지털 클록 데이터 복원회로 133.1. 클록 생성기 153.1.1. 위상 주파수 검출기 163.1.2. 전하 펌프 183.1.3. 전압 제어 발진기 213.2. 클록 데이터 복원회로 233.2.1. 저전력을 위해 제안된 샘플러와 위상 에러 검출기 243.2.2. 위상 회전기 304. 모의 실험 및 측정결과 324.1. 모의 실험 324.1.1. 클록 생성기 324.1.2. 클록 데이터 복원회로 344.2. 측정결과 374.2.1. 클록 생성기 404.2.2. 클록 데이터 복원회로 425. 결 론 45참 고 문 헌 46
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