지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.6
- 발행연도
- 2024.12
- 수록면
- 501 - 510 (10page)
- DOI
- 10.5573/JSTS.2024.24.6.501
이용수
초록· 키워드
오류제보하기
A high-speed receiver including an auto- skew calibration circuit for 10 Gb/s mobile industry processor interface (MIPI) D-PHY is proposed to support data communication of high-performance cameras using four data lanes and one clock lane. The proposed auto-skew calibration circuit, consisting of a delay line and skew control blocks for data and clock, supports skew calibration for predetermined training data while also supporting skew calibration for random data not defined in the MIPI D-PHY. It performs a phase comparison between the clock and the data for skew calibration, which uses only the rising edge of the data instead of the rising and falling edges of the clock as the reference signal. The delay line used in the skew calibration circuit uses a delay cell consisting of three NANDs consuming 1.41 mW at full delay. The proposed MIPI D-PHY receiver including the auto-skew calibration circuit is designed by using a 28-nm CMOS process with a supply voltage of 1.0 V. The proposed MIPI D-PHY receiver circuit receives 2.5 Gb/s of data per data lane for a total of 10 Gb/s of data and consumes 0.4 mW/Gbps/lane. The proposed auto skew calibration circuit improves the data skew from 148 ps to 19 ps and from 230 ps to 18 ps for the predetermined training and random data, respectively.
목차
Abstract
I. INTRODUCTION
II. DESIGN OF 10 GB/S MIPI D-PHY RECEIVER WITH AUTO-SKEW CALIBRATION
III. SIMULATION RESULTS OF PROPOSED MIPI D-PHY RECEIVER WITH AUTO-SKEW CALIBRATION
IV. CONCLUSIONS
REFERENCES
참고문헌 (15)
참고문헌 신청
E. Yeung and M. A. Horowitz, "A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation," IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1619-1628, Nov. 2000.
Yi-Ming Wang and Jinn-Shyan Wang, "A low-power half-delay-line fast skew-compensation circuit," IEEE Journal of Solid-State Circuits, vol. 39, no. 6, pp. 906-918, June 2004.
MIPI Alliance Specification for D-PHY, version, 1.2, Aug. 2014.
MIPI Alliance Specification for D-PHY, version, 2.0, Nov. 2015.
P. -H. Lee and Y. -C. Jang, "A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface," IEEE Transactions on Consumer Electronics, vol. 65, no. 4, pp. 484-492, Nov. 2019.
Yi-Ming Wang and Jinn-Shyan Wang, "A low-power half-delay-line fast skew-compensation circuit," IEEE Journal of Solid-State Circuits, vol. 39, no. 6, pp. 906-918, June 2004.
MIPI Alliance Specification for D-PHY, version, 1.2, Aug. 2014.
MIPI Alliance Specification for D-PHY, version, 2.0, Nov. 2015.
P. -H. Lee and Y. -C. Jang, "A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface," IEEE Transactions on Consumer Electronics, vol. 65, no. 4, pp. 484-492, Nov. 2019.
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