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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2023.5
- 수록면
- 3,346 - 3,350 (5page)
이용수
초록· 키워드
오류제보하기
Inverters with a parallel structure are an effective solution to increase the system"s power capacity. However, low-frequency zero-sequence circulating current (ZSCC), which degrades the output current quality and increases the power losses, might arise due to the unequal zero-sequence voltages generated by parallel inverters. To overcome this issue, this paper presents an improved pulse width modulation (PWM) method to suppress the zero-sequence circulating current in parallel three-phase inverters. The proposed modulation method can be simply and flexibly embedded into the classical voltage-oriented control (VOC) architecture with minimum modification, and ZSCC can be effectively regulated around zero. The proposed solution removes the zero-sequence loop controller, simplifying the control structure and making it very friendly to implement from the engineering perspective. In the end, experimental results validate the effectiveness of the proposed method.
목차
Abstract
I. INTRODUCTION
II. MODELING OF THE ZERO-SEQUENCE LOOP
III. IMPROVED PWM METHOD WITH ZSCC SUPPRESSION CAPABILITY
IV. SIMULATION AND EXPERIMENTAL VALIDATION
V. CONCLUSION
REFERENCES
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