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논문 기본 정보

자료유형
학술대회자료
저자정보
Radhika Sarda (Nanyang Technological University) Ezequiel Rodriguez (Nanyang Technological University) Naga Brahmendra Gorla Yadav (Indian Institute of Technology Palakkad) Glen G. Fariva (University of Melbourne) Josep Pou (Nanyang Technological University) V. B. Sriram (Nanyang Technological University) Anshuman Tripathi (University of Melbourne)
저널정보
전력전자학회 ICPE(ISPE)논문집 ICPE 2023-ECCE Asia
발행연도
2023.5
수록면
2,530 - 2,535 (6page)

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In the modular three-stage solid-state transformer (SST), each phase is integrated with large dc-link capacitors as energy buffers, to filter the second harmonic capacitor voltage ripple generated due to single-phase power processing. Although large dc-link capacitors reduce the coupling between stages of the SST and simplify the controller design, they compromise the reliability, safety and power density of the SST. Accordingly, a low-capacitance SST is desirable to address these challenges. To provide a high-bandwidth control for the low-capacitance SST, this paper proposes using an analytic filtering scheme rather than the low-pass filters used in conventional SST control schemes. A portion of the second harmonic power ripple in the high-voltage dc-link capacitors is processed by the SST s dc-dc stage to facilitate the use of low capacitance. The effectiveness of the proposed control is demonstrated through a simulation study in PLECS.

목차

Abstract
Ⅰ. INTRODUCTION
Ⅱ. CONVENTIONAL CONTROL OF SST
Ⅲ. PROPOSED CONTROL OF SST
Ⅳ. SIMULATIONS
Ⅴ. CONCLUSION
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