지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.2
- 발행연도
- 2024.4
- 수록면
- 69 - 75 (7page)
- DOI
- 10.5573/JSTS.2024.24.2.69
이용수
초록· 키워드
오류제보하기
The performance optimization of a circuit in a short time is one of the important issues for IC testing. Traditional methods depend on domain knowledge and exhaustive search (ES) for feasible parameters. In this paper, we proposed the suboptimal control of the integrated phase noise (IPN) characteristics of RF phase lock loop (PLL) using a Bayesian optimization. For data acquisition, we designed an autonomous measurement platform based on general purpose interface bus (GPIB) and Python. Using our algorithm, we achieved performance within around 3 dB of the optimal at the 95th percentile and reduced the search time for optimal parameters by at least 98.75% compared to the ES method.
목차
Abstract
I. INTRODUCTION
II. MEASUREMENT OPTIMIZATION
III. MEASUREMENTS
IV. CONCLUSION
REFERENCES
참고문헌 (8)
참고문헌 신청
G. Haralampos, et. al, “Machine learning applications in IC testing,” European Test Symposium, 2018, ETS 2018, 23rd, pp. 1-10, Jun., 2018.
K. Shu and E. Sánchez-Sinencio, CMOS PLL Synthesizers: Analysis and Design. Springer New York, NY, 2005.
K. Wang, A. Swaminathan, and I. Galton, “Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL,” Solid-State Circuits, IEEE Journal of, Vol. 43, No. 12, pp. 2787-2797, Dec., 2008.
S. Bae, K. Kim, and I. Hwang. “An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect,” IEICE Electronics Express, Vol. 11, No. 15, pp. 1-8, Aug., 2014.
P. Frazier, “A tutorial on Bayesian optimization,” arXiv preprint, arXiv:1807.02811, 2018.
K. Shu and E. Sánchez-Sinencio, CMOS PLL Synthesizers: Analysis and Design. Springer New York, NY, 2005.
K. Wang, A. Swaminathan, and I. Galton, “Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL,” Solid-State Circuits, IEEE Journal of, Vol. 43, No. 12, pp. 2787-2797, Dec., 2008.
S. Bae, K. Kim, and I. Hwang. “An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect,” IEICE Electronics Express, Vol. 11, No. 15, pp. 1-8, Aug., 2014.
P. Frazier, “A tutorial on Bayesian optimization,” arXiv preprint, arXiv:1807.02811, 2018.
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