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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.6
- 발행연도
- 2023.12
- 수록면
- 367 - 374 (8page)
- DOI
- 10.5573/JSTS.2023.23.6.367
이용수
초록· 키워드
오류제보하기
A high-speed broadband programmable frequency divider chip is designed and implemented in 0.18 μm SiGe BiCMOS process. The chip is based on the 2/3 dual-mode frequency divider, and integrates high-speed logic operation and reset control in the flip-flop to achieve a wide range of continuous integer frequency division ratio. Taking SCFL and CML DFF as basic units, it realizes wideband operation and obtains a good input sensitivity range. The test results demonstrate that the operating frequency covers 0.1 GHz to 16 GHz. The frequency divider achieves 1-511 continuous frequency division. The output signal phase noise of the 1 GHz input is -153.7 dBc/Hz @ 100 kHz offset in divide-by-8 mode.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE DESIGN
Ⅲ. CIRCUIT DESIGN
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
Z. Chen, Y. Zhang, X. Tang, J. Li, F. Huang and N. Jiang, “Design of low power consumption, high-speed and wide division ratio range programmable frequency divider,” in 2020 5th International Conference on Integrated Circuits and Microsystems (ICICM 2020)
M. Subhanil and K. J. Sanjay, “Design of a low power high speed CML-based divide-by-5 prescaler in 180 nm process technology,” in Proceedings of 2020 IEEE Applied Signal Processing Conference (ASPCON 2020), 2020, pp. 303-307.
S. K. Saw, M. Maiti and P. Meher, “Design and analysis of dual modulus prescaler circuit for frequency synthesizer,” in Proceedings - 2019 IEEE International Symposium on Smart Electronic Systems (iSES 2019), 2019, pp. 185-188.
Z. Chen, Z. Wang, H. Liu and W. Wang, “A 26-44 GHz programmable frequency divider for wideband MM-wave,” in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2019), 2019, p. 8754127.
F. Centurelli, G. Scotti, A. Trifiletti and G. Palumbo, “Design of low-voltage power efficient frequency dividers in folded MOS current mode logic,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 2, pp. 680-691, 2021.
M. Subhanil and K. J. Sanjay, “Design of a low power high speed CML-based divide-by-5 prescaler in 180 nm process technology,” in Proceedings of 2020 IEEE Applied Signal Processing Conference (ASPCON 2020), 2020, pp. 303-307.
S. K. Saw, M. Maiti and P. Meher, “Design and analysis of dual modulus prescaler circuit for frequency synthesizer,” in Proceedings - 2019 IEEE International Symposium on Smart Electronic Systems (iSES 2019), 2019, pp. 185-188.
Z. Chen, Z. Wang, H. Liu and W. Wang, “A 26-44 GHz programmable frequency divider for wideband MM-wave,” in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2019), 2019, p. 8754127.
F. Centurelli, G. Scotti, A. Trifiletti and G. Palumbo, “Design of low-voltage power efficient frequency dividers in folded MOS current mode logic,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 2, pp. 680-691, 2021.
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