지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.4
- 발행연도
- 2023.8
- 수록면
- 215 - 227 (13page)
- DOI
- 10.5573/JSTS.2023.23.4.215
이용수
초록· 키워드
오류제보하기
In this work, circuit-level benchmarks were performed on Copper(Cu), Tungsten(W), Cobalt(Co), Ruthenium(Ru), and Doped-multilayer-graphene (DMLG), which are various metallic material options applicable to the wire process at the late semiconductor process nodes. For the transistor, a multi-nanosheet field-effect-transistor (mNS-FET) with gate-all-around (GAA) technology was used, and the power and performance characteristics of the inverter ring oscillator circuit were analyzed assuming a 3 nm process node. In addition, various wire metal options for circuit layout were evaluated by varying fan-out number and wire length. As a result, the speed is fastest for Co and the speed reduction is smallest for DMLG in FO1 50CPP.
목차
Abstract
I. INTRODUCTION
II. PATH-FINDING PROCESS-DESIGN-KIT (PDK) SETUP AND LOGIC INTEGRATED CIRCUIT ANALYSIS RESULTS
III. CONCLUSIONS
REFERENCES
참고문헌 (28)
참고문헌 신청
Nagy, Daniel, et al. "FinFET versus gate-all-around nanowire FET: performance, scaling, and variability." IEEE Journal of the Electron Devices Society 6 (2018): 332-340.
Das, Uttam Kumar, and Tarun Kanti Bhattacharyya. "Opportunities in device scaling for 3-nm node and beyond: FinFET versus GAA-FET versus UFET." IEEE Transactions on Electron Devices 67.6 (2020): 2633-2638..
Razavieh, Ali, Peter Zeitzoff, and Edward J. Nowak. "Challenges and limitations of CMOS scaling for FinFET and beyond architectures." IEEE Transactions on Nanotechnology 18 (2019): 999-1004.
Loubet, N., et al. "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET." 2017 Symposium on VLSI Technology. IEEE, 2017.
Bae, Geumjong, et al. "3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications." 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018.
Das, Uttam Kumar, and Tarun Kanti Bhattacharyya. "Opportunities in device scaling for 3-nm node and beyond: FinFET versus GAA-FET versus UFET." IEEE Transactions on Electron Devices 67.6 (2020): 2633-2638..
Razavieh, Ali, Peter Zeitzoff, and Edward J. Nowak. "Challenges and limitations of CMOS scaling for FinFET and beyond architectures." IEEE Transactions on Nanotechnology 18 (2019): 999-1004.
Loubet, N., et al. "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET." 2017 Symposium on VLSI Technology. IEEE, 2017.
Bae, Geumjong, et al. "3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications." 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018.
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