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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국센서학회 센서학회지 센서학회지 제26권 제4호
- 발행연도
- 2017.7
- 수록면
- 292 - 296 (5page)
- DOI
- http://dx.doi.org/10.5369/JSST.2017.26.4.292
이용수
초록· 키워드
오류제보하기
It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a tran- sistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability(aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow downa transistor’s switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, thetransistor aging is emerging as a circuit designer’s problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.
목차
등록된 정보가 없습니다.
참고문헌 (8)
참고문헌 신청
B. Paul / 2006 / Temporal Performance Degradation Under NBTI:Estimation And Design For Improved Reliability Of Nanoscale Circuits 1:1~6
Intel / 3-D, 22nm: New Technology Delivers An Unprecedented Combination of Performance and Power Efficiency
Mostafa, H / 2012 / NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias / Semiconductor Manufacturing, IEEE Transac-tions on 25(3):460
S. V. Kumar / 2009 / Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits / Proc. IEEE ASP-DAC :284~289
F. Arnaud / 2008 / 32nm general purpose bulk CMOS technology for high performance applications at low voltage / IEEE IEDM’08 :1~4
Intel / 3-D, 22nm: New Technology Delivers An Unprecedented Combination of Performance and Power Efficiency
Mostafa, H / 2012 / NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias / Semiconductor Manufacturing, IEEE Transac-tions on 25(3):460
S. V. Kumar / 2009 / Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits / Proc. IEEE ASP-DAC :284~289
F. Arnaud / 2008 / 32nm general purpose bulk CMOS technology for high performance applications at low voltage / IEEE IEDM’08 :1~4
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