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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국정보통신학회JICCE Journal of information and communication convergence engineering Journal of information and communication convergence engineering Vol.17 No.4
- 발행연도
- 2019.12
- 수록면
- 285 - 289 (5page)
이용수
초록· 키워드
오류제보하기
A 1.9-GHz linear CMOS power amplifier is presented. An adaptive bias circuit (ABC) that utilizes an AC ground to detect the power level of the input signal is proposed to enhance the linearity and efficiency of the power amplifier. The ABC utilizes the second harmonic component as the input to mitigate the distortion of the fundamental signal. The input power level of the ABC was detected at the AC ground located at the V<SUB>DD</SUB> node of the power amplifier. The output of the ABC was fed into the inputs of the power stage. The input signal distortion was mitigated by detecting the input power level at the AC ground. The power amplifier was designed using a 180 nm RFCMOS process to evaluate the feasibility of the application of the proposed ABC in the power amplifier. The measured output power and power-added efficiency were improved by 1.7 dB and 2.9%, respectively.
목차
Abstract
I. INTRODUCTION
II. ADAPTIVE BIASING TECHNIQUE USING AC GROUND
III. DESIGN OF THE PROPOSED POWER AMPLIFIER
IV. EXPERIMENTAL RESULTS
V. CONCLUSION
REFERENCES
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