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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2022.12
- 수록면
- 1,020 - 1,033 (14page)
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In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1 μs. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, -0.676 μs. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 μs for all MI traffic with less than 10% of transmission overhead.
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