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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.6
- 발행연도
- 2021.12
- 수록면
- 381 - 389 (9page)
- DOI
- 10.5573/JSTS.2021.21.6.381
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초록· 키워드
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In this study, we present variations in transfer characteristics and memory performances caused by work-function variation (WFV) in the metal gate of a one-transistor dynamic random-access memory cell based on a gate-all-around junctionless field-effect transistor (GAA-JLFET). To investigate the influence of WFV, we simulated 200 samples of GAA-JLFETs. The samples had different transfer characteristics depending on the metal grain granularity. In addition, we calculated and analyzed the mean and standard deviations for the transfer characteristics. Further, the memory performances were analyzed using two extreme cases with the highest and lowest threshold voltage (V<SUB>th</SUB>) as examples. When WFV was not considered, the current ratio was 108, and retention time was more than 10 ms. Meanwhile, when WFV was considered, the current ratio was 10² and 10⁴, and the retention time was reduced to 0.051 ms and 2.2 ms, respectively. These results showed that WFV affected not only the transfer characteristics in GAA-JLFET but also the memory performances; it could adversely affect the reliability of the memory device.
목차
Abstract
I. INTRODUCTION
II. DEVICE STRUCTURE AND SIMULATION METHOD
III. RESULTS AND DISCUSSION
IV. CONCLUSIONS
REFERENCES
참고문헌 (17)
참고문헌 신청
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Zhang, J., Yuan, J. S., and Ma, Y. “Modeling short channel effect on high-k and stacked-gate MOSFETs.” Solid-state electronics, vol. 44, no. 11, pp. 2089-2091. Nov. 2000
Tsormpatzoglou, A., Dimitriadis, C. A., Clerc, R., Rafhay, Q., Pananakakis, G., and Ghibaudo, G. “Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs.” IEEE Transactions on Electron devices, vol. 54, no. 8, pp. 1943-1952. Aug. 2007
Khan, M. U., Arshad, A., Ume, S., Bukhari, R., Samer, A., and Tariq, F. “Nanoscale CMOS Scaling Trends, Challenges and Their Solutions.” ICAME21, International Conference on Advances in Mechanical Engineering, Pakistan, pp. 1-10. Aug. 2021
Takeuchi, H., Wong, H. Y., Ha, D., and King, T. J. “Impact of oxygen vacancies on high-κ gate stack engineering.”. IEEE International Electron Devices Meeting, pp. 829-832. Dec. 2004.
Zhang, J., Yuan, J. S., and Ma, Y. “Modeling short channel effect on high-k and stacked-gate MOSFETs.” Solid-state electronics, vol. 44, no. 11, pp. 2089-2091. Nov. 2000
Tsormpatzoglou, A., Dimitriadis, C. A., Clerc, R., Rafhay, Q., Pananakakis, G., and Ghibaudo, G. “Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs.” IEEE Transactions on Electron devices, vol. 54, no. 8, pp. 1943-1952. Aug. 2007
Khan, M. U., Arshad, A., Ume, S., Bukhari, R., Samer, A., and Tariq, F. “Nanoscale CMOS Scaling Trends, Challenges and Their Solutions.” ICAME21, International Conference on Advances in Mechanical Engineering, Pakistan, pp. 1-10. Aug. 2021
Takeuchi, H., Wong, H. Y., Ha, D., and King, T. J. “Impact of oxygen vacancies on high-κ gate stack engineering.”. IEEE International Electron Devices Meeting, pp. 829-832. Dec. 2004.
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