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논문 기본 정보

자료유형
학술저널
저자정보
Nam Hwi Jeong (Korea Aerospace University) Choon Sik Cho (Korea Aerospace University)
저널정보
한국전자파학회JEES Journal of Electromagnetic Engineering And Science Journal of Electromagnetic Engineering And Science Vol.14 No.4
발행연도
2014.12
수록면
376 - 381 (6page)

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초록· 키워드

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We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout(LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a 0.35-㎛ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as 9 ㎲ for an input variation of 4.7-6 V. In addition, an output capacitor of 100pF was realized on chip integration.

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. CIRCUIT DESIGN AND ANALYSIS
Ⅲ. SIMULATION AND MEASUREMENT RESULTS
Ⅳ. CONCLUSIONS
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