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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 한국정보디스플레이학회 한국정보디스플레이학회 International Meeting 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
- 발행연도
- 2007.1
- 수록면
- 1,185 - 1,188 (4page)
이용수
초록· 키워드
오류제보하기
The address discharge characteristics by the various scan-low and common-bias voltages are investigated based on measured address discharge time lags and $V_t$ close-curve analysis. The scan-low voltages are changed under the same voltage difference between the X and Y electrodes during an address period. As the voltage difference between the scan and address electrodes is increased during an address period, the address discharge time lag is shortened but the background luminance is increased. It is found that the improved address discharge characteristics is caused by the effect of the higher external applied voltage during an address period than the accumulated wall charges during a reset period and the high background luminance can be prevented by applying an address-bias voltage during a rising-ramp period and low reset voltage.
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