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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2013.1
- 수록면
- 255 - 264 (10page)
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Resolving of memory access latency is one of the most important problems in modern embedded system design. Recently, tons of studies are presented to reduce and hide the access latency. Burst/page data transfer modes are representative hardware techniques for achieving such purpose. The burst data transfer capability offers an average access time reduction of more than 65 percent for an eight-word sequential transfer. However, solution of utilizing such burst data transfer to improve memory performance has not been accomplished at commercial level. Therefore, this paper presents a new technique that provides the maximum utilization of burst transfer for memory accesses with local variables in code by reorganizing variables placement.
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참고문헌 (14)
참고문헌 신청
ARM / 2007 / ARM architecture reference manual
ARM / 2009 / CoreLink DMA Controllers / Technical reference manual
C. Lee / 1997 / MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems / Proceedings on IEEE International Symposium of Microarchitecture : 330 ~
D. Bartely / 1992 / Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes / Software Practice & Experience 22 (2) : 101 ~ 110
Fujitsu / 2008 / FR80S/T series DMA access speed / hardware manual AN07-00156-1E
ARM / 2009 / CoreLink DMA Controllers / Technical reference manual
C. Lee / 1997 / MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems / Proceedings on IEEE International Symposium of Microarchitecture : 330 ~
D. Bartely / 1992 / Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes / Software Practice & Experience 22 (2) : 101 ~ 110
Fujitsu / 2008 / FR80S/T series DMA access speed / hardware manual AN07-00156-1E
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