지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2011.1
- 수록면
- 345 - 359 (15page)
이용수
초록· 키워드
오류제보하기
In high performance embedded systems, the use of multiple on-chip memories is an essential architectural feature for exploiting inherent parallelism in multimedia applications. This feature allows multiple data accesses to be executed in parallel. However, it remains difficult to effectively exploit of multiple on-chip memories. The successful use of this architecture strongly depends on how to efficiently detect and exploit memory parallelism in target applications. In this paper, we propose a technique based on a linear array access descriptor [1], which is generated from profiled data, to detect and exploit memory parallelism. The proposed technique tackles an array reorganization problem to maximize memory parallelism in multimedia applications. We present preliminary experiments applying the proposed technique onto a representative coarse grained reconfigurable array processor (CGRA) with multimedia kernel codes. Our experimental results demonstrate that our technique optimizes data placement by putting independent data on separate storage. The results exhibit 9.8% higher performance on average compared to the existing method.
목차
등록된 정보가 없습니다.
참고문헌 (23)
참고문헌 신청
/ / ICD-C compiler framework,University of Dortmund
A.Hatanaka / 2007 / A modulo scheduling algorithm for a coarse-grain reconfigurable array template / Proceedings of the IPDPS’07 : 1 ~ 8
B. Mei / 2003 / Adres: An architecture with tightly coupled vliw processor and coarse grained reconfigurable matrix / Proceeding of Field Programmable Logic, FPL’03 : 61 ~ 70
Chau wen Tseng / 1995 / Compiler optimizations for eliminating barrier synchronization / ACM SIGPLAN : 144 ~ 155
Daniel Edward Lenoski / 1992 / The design and analysis of DASH:a scalable directory-based multiprocessor / 박사 / Stanford university
A.Hatanaka / 2007 / A modulo scheduling algorithm for a coarse-grain reconfigurable array template / Proceedings of the IPDPS’07 : 1 ~ 8
B. Mei / 2003 / Adres: An architecture with tightly coupled vliw processor and coarse grained reconfigurable matrix / Proceeding of Field Programmable Logic, FPL’03 : 61 ~ 70
Chau wen Tseng / 1995 / Compiler optimizations for eliminating barrier synchronization / ACM SIGPLAN : 144 ~ 155
Daniel Edward Lenoski / 1992 / The design and analysis of DASH:a scalable directory-based multiprocessor / 박사 / Stanford university
이 논문의 저자 정보
최근 본 자료
댓글(0)
0