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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2013.1
- 수록면
- 17 - 24 (8page)
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In this paper, we present a multi-core processor including multimedia specific instructions to process multimedia data efficiently in the mobile environment. Multimedia specific instructions exploit subword level parallelism (SLP), while the multi-core processor exploits data level parallelism (DLP). These combined parallelisms improve the performance of multimedia processing applications. The proposed multi-core processor including multimedia specific instructions is implemented and tested using a Xilinx ISE 10.1 tool and SoCMaster3 testbed system including Vertex 4 FPGA. Experimental results using a fire detection algorithm show that multimedia specific instructions outperform baseline instructions in the same multi-core architecture in terms of performance (1.2x better), energy efficiency (1.37x better), and area efficiency (1.23x better).
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참고문헌 (10)
참고문헌 신청
A. Gentile / 2004 / Portable Video Supercomputing / IEEE Trans. on Computers 53 (8) : 960 ~ 973
E.B. Bourennane / 2002 / Cost Comparison of Image Rotation Implementations on Static and Dynamic Reconfigurable FPGAs / Proceedings on the International Conference of Acoustics, Sp
J.C. Eble / 2001 / A Generic System Simulator (GENESYS) for ASIC Technology and Architecture beyond 2001 / Proceedings on the International Conference of ASIC : 193 ~ 196
R.B. Lee / 1996 / Subword Parallelism with MAX-2 / IEEE Micro 16 (4) : 51 ~ 59
S.M. Chai / 2000 / Heterogeneous architecture models for interconnect-motivated system design / IEEE Transactions on VLSI Systems 8 (6) : 660 ~ 670
E.B. Bourennane / 2002 / Cost Comparison of Image Rotation Implementations on Static and Dynamic Reconfigurable FPGAs / Proceedings on the International Conference of Acoustics, Sp
J.C. Eble / 2001 / A Generic System Simulator (GENESYS) for ASIC Technology and Architecture beyond 2001 / Proceedings on the International Conference of ASIC : 193 ~ 196
R.B. Lee / 1996 / Subword Parallelism with MAX-2 / IEEE Micro 16 (4) : 51 ~ 59
S.M. Chai / 2000 / Heterogeneous architecture models for interconnect-motivated system design / IEEE Transactions on VLSI Systems 8 (6) : 660 ~ 670
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