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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2011.1
- 수록면
- 35 - 41 (7page)
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초록· 키워드
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Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA.
The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
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참고문헌 (13)
참고문헌 신청
Chengalva, M. / 2000 / Effect of Circuit Board Flexure on Flip Chips before Underfill / Proc. 50th Electronic Components and Technology Conference
JEDEC Standard JESD22-200-BAA0 / 2001 / Subassembly Mechanical Shock
JEDEC Standard JESD22-B111 / 2003 / Board Level Drop Test Method of Components for Handheld Electronic Products
Luan, J.E. / 2003 / Modal Analysis and Dynamic Responses of Board Level Drop Test / 5th EPTC Conference Proc : 233 ~ 243
Luan, J.E. / 2004 / Novel Board Level Drop Test Simulation using Implicit Transient Analysis with Input-G Method / 6th EPTC Conference Proc
JEDEC Standard JESD22-200-BAA0 / 2001 / Subassembly Mechanical Shock
JEDEC Standard JESD22-B111 / 2003 / Board Level Drop Test Method of Components for Handheld Electronic Products
Luan, J.E. / 2003 / Modal Analysis and Dynamic Responses of Board Level Drop Test / 5th EPTC Conference Proc : 233 ~ 243
Luan, J.E. / 2004 / Novel Board Level Drop Test Simulation using Implicit Transient Analysis with Input-G Method / 6th EPTC Conference Proc
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